Electronic systems have grown in complexity over the years. Modern electronic systems are often built from tens or even hundreds of millions of transistors, which make them difficult and expensive to design and validate. The market also drives an ever-increasing demand for performance, advanced feature sets, system versatility, and a variety of other rapidly changing system requirements. Competing demands often introduce contradictory design requirements into the design process. System designers are required to make significant tradeoffs in performance, physical size, architectural complexity, power consumption, heat dissipation, fabrication complexity, and cost, to name a few, to try to best meet the design requirements. Each design decision exercises a profound influence on the resulting electronic system. To handle such electronic system complexity, designers create specifications around which to design their electronic systems. The specifications attempt to balance the many disparate demands being made of the electronic systems in order to contain the exploding design complexity.
Logic system designers develop the needed system specification to which proposed designs must conform. Comparison of proposed designs to the specification helps ensure that the designs meet critical system objectives. This process of comparison is called verification. Logic systems are often described at a variety of levels of abstraction, from low-level transistor layouts to high-level description languages. Most designers describe and design their electronic systems at a high-level of abstraction using an IEEE Standard hardware description language (HDL) such as Verilog™, SystemVerilog™, or VHDL™, as a high-level HDL is often easier for designers to understand, especially for a vast system, and can describe highly complex concepts that are difficult to grasp using a lower level of abstraction. The HDL description can later be converted into any of numerous other levels of abstraction as desired by the developers. For example, a high-level description can be converted to a logic-level description such as a register-transfer language (RTL), a gate-level (GL) description, a layout-level description, or a mask-level description. Each lower level of abstraction introduces more detail into the design description.
Many of the steps in a design automation chain can be deemed to be correct by construction. That is, the lower-levels of abstraction are generated automatically by computer, derived from a design library, or created by another design automation technique. For example, the generation of a gate-level description from a logic-level description can be easily verified as being equivalent due to a one-to-one correspondence between a construct in the RTL and a set of gates in the gate level description. But other steps are more difficult to verify. In some cases, a section of the design is hand-designed to optimize for certain parameters, and there is not necessarily a one-to-one correspondence between two different abstractions of the design. In other cases, the complexity is such that the automated tool cannot easily verify that a design's output is equivalent to its input. Even without correct-by-construction verification available, the resulting lower-level designs still must be capable of matching the requirements of the system specification and provide the equivalent logic function.